SoC-e has a strong R&D activity and maintains a strong link the University of the Basque Country (UPV/EHU) and it collaborates with different Universities and Research Centers to contribute to the research community enhancing the technologies related to reliable networking, synchronization and security.
The following publication list summarizes some of the publications released with SoC-e support:
Title
Window violation and jitter calculations using Time Aware Shaper in a TSN network.
Abstract
This paper presents a TSN platform from SoC-e, to which an IEEE 802.1Qbv and IEEE 802.1AS-2020 test case from SoC-e’s TSN test plan will be performed. It aims to prove the proper performance of Time Aware Shaper in a TSN network. In this paper, the test procedure, configuration, test setup and results needed to validate the jitter and window violation in a TSN network are presented. The DUTs used in this test are RELY-TSN12 and RELY-10TSN12 from RELYUM by SoC-e. Meanwhile, the test station used are Paragon-X from Calnex and Novus ONE PLUS from Keysight.
2020 Scientific-Technical Contributions:
XXXV Design of Circuits and Integrated Systems Conference (DCIS 2020)
Title
Secure Critical Traffic of the Electric Sector over Time-Sensitive Networking
Abstract
The convergence of operational technology (OT) and information technology (IT) in the same network is essential for upcoming digitized scenarios, such as the Electric Sector, Smart-Grid, and Substation Automation Systems (SAS). The typical separation of these two areas in the traditional Ethernet standard is increasingly disappearing. Furthermore, security requirements must be fulfilled in the involved systems and infrastructures. It is the case of the Electric Sector, which is aware of this necessity and it is trying to protect all digitized data streams, even the most critical one with tight real-time requirements. The technology that allows this OT/IT integration is Deterministic Ethernet. The standard and interoperable Deterministic Ethernet alternative is named Time-Sensitive Networking (TSN) standard. TSN offers a convergent, interoperable, deterministic, and uniform network. However, it lacks from security mechanisms for real-time traffic. This paper presents a concept-proof work used to prove that the hard real-time traffic used in the power substations can be protected using wire-speed cryptography and data-flow hardware processing approach.
Title
Synchronizing NTP Referenced SCADA Systems Interconnected by High-availability Networks
Abstract
Because of its reliability demands, Industry has not previously trusted in commercial Ethernet for data communication, despite being the cheapest option and the de facto standard. Nevertheless, during the last years, some technological innovations have enhanced its safety and predictability so much, that Ethernet has turned into the industrial network. Critical sectors, such as Electric Power, with high-availability and strict timing requirement, have taken advantage of these developments,after having driven them.
To allow some other crucial applications to get benefit from these innovations, the next step is providing system integrators with validated and compatible quipment. For this purpose,our paper presents a Smart PCIe card that delivers a common main clock throughout the industrial data network. Our design supports zero-delay recovery sub-standards (HSR and PRP), and autonomously manages Precise-Time-Protocol (PTP or IEEE 1588), for accurate synchronization over Ethernet. Besides, the board integrates a clock protocol gateway, so that legacy systems, not compatible with the PTP reference, can be synchronously attached. As an example, the presented use-case synchronizes a SCADA system by taking the time reference from the Windows Operating system that is synchronized using the native Network Time Protocol (NTP) slave. This clock is provided by the NTP master embedded in the PCIe card.
TSN/A Conference 2020. Technology and Applications
Title
Taking benefit from TSN in Automotive and in Time-aware Wireless set-ups
Abstract
Time-Sensitive Networking (TSN) is evolving at different speeds. While the equipment vendors start to offer to the market TSN products based on the most stable and tested features, the technology providers push actions for evaluating the newest TSN capabilities.
This presentation presents two innovative use-cases and pilots where SoC-e TSN Technology has been applied. The first one, presents a DENSO AUTOMOTIVE Deutschland GmbH comprehensive TSN setup for Automotive Applications. The second one, focused on factory automation, has been developed by Ikerlan Research Center combining wired TSN networks and Wireless ones sharing the same synchronization layer.
2019 Scientific-Technical Contributions:
TSN/A Conference 2019. Technology and Applications
Title
DDS over TSN to Support NATO Generic Vehicle Architecture (NGVA) for Land Systems
Abstract
In collaboration with RTI, a Connext DDS implementation over TSN is presented. The new generation of military vehicles is evolving towards standardization. As an example, NATO Generic Vehicle Architecture (NGVA) is an approach to platform design and integration. In NGVA, the information is based on DDS middleware. DDS profiles regulate the message transfer using advanced QoS parameters. However, all data types and communication layers finally rely on an Ethernet Data Link Layer. TSN in combination with DDS can ensure the deterministic of the data delivery while the overall complexity and cost of the final implementation can be drastically reduced.
Title
Abstract
This contribution presents a digital factory use-case for a redundant TSN implementation on a pilot section of a modern manufacturing center for the Aeronautics sector located in Europe. The set-up includes IEEE 802.1CB-2007 support from two different vendors, Xilinx for the TSN end-points devices and SoC-e for the bridges and edge-computing equipment. In this presentation, the results of the first stage of the project are presented: the behavioral of the high-level protocols over redundant Ethernet, the configuration mechanisms and models used for the configuration and a comparison to the same set-up based on HSR.
IEEE Internet of Things Journal
Title
Smart Sensor: SoC architecture for the Industrial Internet of Things
Abstract
Nowadays, the concept of intelligent manufacturing is being introduced, based on the integration of new advanced technologies such as the Internet of Things (IoT), distributed control, data analysis, and cyber-security in the manufacturing area, with the aim of improving manufacturing processes and the articles produced. In this sense, new intelligent devices (Smart Sensors) should be developed that integrate several detection methods (sensors), real-time data analysis and wired and/or wireless connectivity. The main contribution of this paper is the design, implementation and experimental verification of an architecture of a Smart Sensor that satisfies the operational requirements needed by the Industrial Internet of Things (IIoT). Considering the software and hardware adaptability that a Smart Sensor
should have, this work takes advantage of the characteristics of the current Field Programmable Gate Arrays (FPGA) and SoC to implement a Smart Sensor for the IIoT. In this sense, the proposed Smart Sensor architecture incorporates real-time operation features, the ability to perform local data analysis, high availability communication interfaces such as High-availability Seamless Redundancy (HSR) and Parallel Redundancy Protocol (PRP), interoperability (industrial protocols) and cyber-security.
The architecture was implemented with hardware available in the market, IP cores and Python libraries developed by third parties. Finally, to validate the applicability of the architecture in the industry, two test environments were implemented. In the first case, interoperability, high availability, synchronization, and local data processing are validated. The second case aims to determine the delay when adding encryption (cyber-security) in layer 2 communications.
2019 Tech Use Cases (in collaboration with our partner Relyum):
Title
An Easy Way to Start Working in the New Generation Ethernet: Time-Sensitive Networking (TSN)
Abstract
The digital factory demands interoperability and simplicity in communications. TSN is the new generation Ethernet designed expressly to meet those requirements. Although the introduction of TSN will be progressive depending on the sector, some critical ones like Railway or Aerospace, are adopting TSN as the standard IT/OT network in their new platforms.
In this paper, an intelligent TSN NIC card is presented. It embeds all the complexity required to connect a standard PC to a TSN network without the need of installing any special software on the host. This approach enables the use of typical Industrial applications and software under TSN, such as SCADA, MES,
OPC (UA), MTConnect, etc.
Link
Title
Seamless Merging of PRP and HSR Networks without External RedBoxes
Abstract
The Industry is converging on Ethernet. During latest year, some technology innovations have emerged to enhance the resilience of standard Ethernet network and to use it as a common link layer for Operation and Information technologies. Critical sectors, like the Electric one, with high-availability and strict timing requirement have pushed these developments.
The next step forward to allow diverse applications taking benefit from this innovation is providing to system integrators ready-to-use equipment. In this sense, this paper presents a use-case of a Smart PCIe card model, RELY-SYNC-HSR/PRP-PCIe, from RELY-PCIe product family. This solution supports zero-delay recovery time Ethernet protocols (HSR and PRP) and manages Precise-Time-Protocol (PTP or IEEE 1588) autonomously for accurate time synchronization over Ethernet. Additionally the board integrates the clock
protocol gateway, simplifying the synchronization of legacy systems not compatible with the PTP reference.
As an example, the use-case presented solves a demand of integrators of High-Availability Ethernet networks: A simple interconnection of PRP and HSR Networks. This solution removes the need for additional intermediate RedBox external equipment integration and allows reusing the existing Gateways or PC Scada Systems to manage the packet processing thanks to the dual functionality of DAN and RedBox embedded on RELY-PCIe
Link
Title
Abstract
The Industry is converging on Ethernet. During latest year, some technology innovations have emerged to enhance the resilience of standard Ethernet network and to use it as a common link layer for Operation and Information technologies. Critical sectors, like the Electric one, with high-availability and strict timing requirement have pushed these developments.
The next step forward to allow diverse applications taking benefit from this innovation is providing to system integrators ready-to-use equipment. In this sense, this paper presents a use-case of a Smart PCIe card model, RELY-SYNC-HSR/PRP-PCIe, from RELY-PCIe product family. This solution supports zero-delay recovery time Ethernet protocols (HSR and PRP) and manages Precise-Time-Protocol (PTP or IEEE 1588) autonomously for accurate time synchronization over Ethernet. Additionally the board integrates the clock
protocol gateway, simplifying the synchronization of legacy systems not compatible with the PTP reference.
As an example, the use-case presented solved the synchronization of a SCADA that takes the time reference from NTP synchronized Windows Operation System. This NTP reference is provided by the NTP master embedded on the RELY-PCIe card.
2018 Scientific-Technical Contributions:
XXXIII Design of Circuits and Integrated Systems Conference (DCIS 2018)
Title
System-on-Programmable-Chip AES-GCM implementation for wire-speed cryptography for SAS
Abstract
Communications within modern electric substations are regulated by IEC 61850. This standard lacks security mechanisms that protect the communications, opening the door for possible threads in the form of cyber-attacks. IEC 62351 defines a security extension to protect layer-2 messages with stringent timing requirements. This extension provides data authentication and confidentially making use of an AES-GCM cipher. An extensive analysis of the state of the art in terms of security in the domain of Substation and Automation Systems (SAS) reveals the requirements for implementing the IEC 62351-6. Based on those specifications, a configurable AES-GCM IP core architecture for FPGAs is proposed. After testing the defined IP core, it is compared to academic and commercial alternatives. Results
reveal that the proposed solution meets all the requirements to enable an implementation of IEC 62351-6, being a suitable solution for SAS and the most balanced solution in terms of resource usage and performance.
TSN/A Conference 2018. Technology and Applications
Title
Facing the Security Challenges in TSN
Abstract
The security in Critical Systems is a hot topic. The digitalization process is non-stoppable, and new cyber-threats are emerging due to OT and IT integration. Therefore, a need for protecting real-time critical messages is increasing. TSN is the interoperable deterministic Ethernet solution oriented to multiple sectors like Industry, Energy, Automotive and Aerospace that impose strong security requirements. Although TSN can benefit from many IT world field-proven security mechanisms, new security challenges like cyber-attacks to the synchronization plane and to the real-time traffic need to be taken into account. This contribution reviews these specific issues and proposes some initial workarounds.
Proceedings of ITSF 2018 (Oral Presentation)Title
Protecting Time-aware Real-Time Traffic in the Smart Grid
Abstract
IEC 61850, the standard for the automation of power substations, is enabling an interoperable digitalization of power substations and many Smart-Grid premises. It defines the data models, services and the communication protocols. Since 2004, when the 14 parts of the standard were released, most of the digitalization processes seen in the sector have followed this standard approach. The Precise-Time-Protocol (PTP, IEEE 1588) is also included in this standard for synchronization purposes.
The Electric Sector, from the security point of view, is identified as a Critical System. Power plants and electric substations are considered Critical Infrastructures. Therefore, the digitalization of these premises has included cyber-attacks as potential threats. The protection of PTP and Layer-2 control messages, GOOSE and SMV, needs specific analysis and workarounds. The standard IEC 62351-6 proposes a security extension for GOOSE and SMV messages. However, this Ethernet traffic is 1588-aware and therefore, any solution proposed to secure these kind of messages must take into account not affecting the synchronization plane.
This presentation reviews the proposed security mechanisms for stringent real-time traffic and proposes a solution able to work within 1588-aware networks.
Energies
Title
Secure Protocol and IP Core for Configuration of Networking Hardware IPs in the Smart Grid
Abstract
Nowadays, the incorporation and constant evolution of communication networks in the electricity sector have given rise to the so-called Smart Grid, which is why it is necessary to have devices that are capable of managing new communication protocols, guaranteeing the strict requirements of processing required by the electricity sector. In this context, intelligent electronic devices (IEDs) with network architectures are currently available to meet the communication, real-time processing and interoperability requirements of the Smart Grid. The new generation IEDs include an Field Programmable Gate Array (FPGA), to support specialized networking switching architectures for the electric sector, as the IEEE 1588-aware High-availability Seamless Redundancy/Parallel Redundancy Protocol (HSR/PRP). Another advantage to using an FPGA is the ability to update or reconfigure the design to support new requirements that are being raised to the standards (IEC 61850). The update of the architecture implemented in the FPGA can be done remotely, but it is necessary to establish a cyber security mechanism since the communication link generates vulnerability in the case the attacker gains physical access to the network. The research presented in this paper proposes a secure protocol and Intellectual Property (IP) core for configuring and monitoring the networking IPs implemented in a Field Programmable Gate Array (FPGA).
The FPGA based implementation proposed overcomes this issue using a light Layer-2 protocol fully implemented on hardware and protected by strong cryptographic algorithms (AES-GCM), defined in the IEC 61850-90-5 standard. The proposed secure protocol and IP core are applicable in any field where remote configuration over Ethernet is required for IP cores in FPGAs. In this paper, the proposal is validated in communications hardware for Smart Grids.
InfoPLC+ Magazine #7 Especial Edition BIEMH
Title
Seguridad y Time-Sensitive Networking
Abstract
El desafío de la seguridad y encriptación wirespeed en protocolos de real time en industria es un asunto es de alto interés desde el punto de vista de regulación, estandarización y negocio. Time Sensitive Networking (TSN) es una propuesta integral para una única solución basada en Ethernet determinístico e interoperable que puede ser adoptada en la mayoría de los sectores.
2018 Tech-Use Cases
Title
Implementing Tailored IEEE 1588-aware Ethernet Switches on FPGAs for Mission-Critical Applications
Abstract
The long-term supply, flexibility and integration capabilities of the modern FPGAs and Reconfigurable Platforms have set these devices as the preferred technology for the new embedded devices in Aerospace and Defense market. In the same way, Ethernet technology combined with the use of IEEE 1588 standard for sub-microsecond timing synchronization has simplified the integration and the interoperability among these systems.
Moreover, the latest innovations in this field, like the standard deterministic Ethernet (TSN) or the high-availability standardized protocols (HSR/PRP), are facilitating the engineering of the whole data flow: precise timestamped data acquisition, real-time traffic communication and seamless integration with Edge-computing and IT infrastructures.
In addition, the design of these complete systems has been facilitated by the graphic design tool suites provided by the FPGA vendors. These tools in combination with configurable IP core portfolio allow seamless design of custom time-aware networking and data acquisition devices from a high-level point of view.
SoCe IPs for synchronization and networking are field-proven technology widely used by the companies of these critical sectors to implement added-value equipment and embedded systems. This paper presents some of the technologies involved in these scenarios and illustrates how benefit of IPs and Reconfigurable Devices.
2017 Scientific-Technical Contributions:
Reliability Engineering & System Safety
Title
SEU Emulation in Industrial SoCs combining Microprocessor and FPGA
Abstract
FPGAs (Field-Programmable Gate Array) and FPGA-based SoCs (System-on-chip) are electronic devices which offer high computational performance and low time-to-market for low and medium production volumes. They are gaining popularity in critical sectors, such as automotive, aerospace, avionics and railway, making their reliability evaluation mandatory. FPGAs are notoriously sensitive to SEUs (Single Event Upsets), which are random memory errors provoked by radiation particles. The failure rate of an FPGA varies with the implemented design, depending on the amount of used resources and the implemented redundancy schemes among others. FPGA-based circuits are being used in complex safety-critical engineering systems that are designed in compliance with dependability regulations. This work presents an emulation-based methodology for estimating the failure rate of designs implemented in FPGA SoCs, which is a key data in this scenario.
ENERGIES
Title
MACsec Layer 2 Security in HSR Rings in Substation Automation Systems
Abstract
The smart-grid concept takes the communications from the enclosed and protected
environment of a substation to the wider city or nationwide area. In this environment, cyber security
takes a key role in order to secure the communications. The challenge is to be able to secure the grid
without impacting the latency while, at the same time, maintaining compatibility with older devices
and non secure services. At the lower level, added security must not interfere with the redundancy
and the latency required for the real-time substation automation communications. This paper studies
how to integrate IEEE MAC Security standard (MACsec) in the substation environment, especially
when used in substation system communications that have stringent response time requirements and
zero recovery time as defined in IEC 62439-3.
2016 Scientific-Technical Contributions:
IEEE TRANSACTIONS ON SMART GRID
Title
On the Utilization of System-on-Chip Platforms to Achieve Nanosecond Synchronization Accuracies in Substation Automation Systems
Abstract
A synchronized common sense of time is a key factor for many smart grid applications, such as the sample value process bus operation. The precision time protocol (PTP), as defined in IEEE 1588-2008 standard, is highly recommended for substation communication networks, because it enables synchronization accuracies in the nanoseconds range through conventional Ethernet-based networks. This paper explores the implementation of PTP functionalities on new Xilinx Zynq-7000 all programmable system-on-chip (SoC) device. Different PTP master and slave implementations have been analyzed taking benefit from the flexibility of the SoC all programmable devices. The explored features go from simple only-software versions aided by PTP support of GMACs embedded in the processor section to high accuracy solutions that include custom PTP hardware in the logic section of the device. For each configuration approach, two different experimental setups based on two Zynq commercial low-cost boards has been built, and the protocol performance has been evaluated by measuring time offset between the pulse per second output signals of the master and the synchronized slave. The results obtained from this analysis show excellent accuracy results, with time offsets in the range of 40 ns and standard deviations of less than 10 ns.
Link
2015 Scientific-Technical Contributions:
2015 International IEEE Symposium on Precision Clock Synchronization for Measurement, Control and Communication (ISCPS 2015)
Title
Security Mechanisms to protect IEEE 1588 Synchronization: State of the Art and Trends
Abstract
The limitations of Annex K, as defined in the second version of IEEE 1588 standard, lead the standardization committee to evolve from an integrated security solution to a set of internal and external security mechanisms. The aim of the group is to address different requirements and deployment paradigms of application specific profiles. In this paper, a comparative study of the proposed security solutions within the working group is presented. In addition, a new MACsec use case to provide hop-by-hop group security is introduced.
Link
Title
1588-aware High-Availability Cyber-Physical Production System
Abstract
In this paper, an architecture for High-Availability Cyber-Physical Production Systems with sub-microsecond synchronization capabilities is presented. The proposed CPPS nodes are based on cost-affordable components. These CPPS can deal with most of the challenges set by Industry for a massive adoption of the distributed computing philosophy in critical systems like Smart-Grids or Advanced Manufacturing Plants. In order to measure the resilience and accuracy of the 1588-aware high-availability network composed by these nodes, a concept-proof experimental setup has been developed. As it has been verified, although in a case of network failure, the synchronization recovers automatically and the offset between the master’s and slaves’ PPS signals is maintained below 1 μs.
Link
The Scientific World Journal
Title
Availability Improvement of Layer 2 Seamless Networks Using OpenFlow
Abstract
The network robustness and reliability are strongly influenced by the implementation of redundancy and its ability of reacting to changes. In situations where packet loss or maximum latency requirements are critical, replication of resources and information may become the optimal technique. To this end, the IEC 62439-3 Parallel Redundancy Protocol (PRP) provides seamless recovery in layer 2 networks by delegating the redundancy management to the end-nodes. In this paper, we present a combination of the Software-Defined Networking (SDN) approach and PRP topologies to establish a higher level of redundancy and thereby, through several active paths provisioned via the OpenFlow protocol, the global reliability is increased, as well as data flows are managed efficiently. Hence, the experiments with multiple failure scenarios, which have been run over the Mininet network emulator, show the improvement in the availability and responsiveness over other traditional technologies based on a single active path.
Link
Computer and Electrical Engineering
Title
Using Software Defined Networking to manage and control IEC 61850-based systems
Abstract
Smart Grid makes use of Information and Communications Technology (ICT) infrastructures for the management of the generation, transmission and consumption of electrical energy to increase the efficiency of remote control and automation systems. One of the most widely accepted standards for power system communication is IEC 61850, which defines services and protocols with different requirements that need to be fulfilled with traffic engineering techniques. In this paper, we discuss the implementation of a novel management framework to meet these requirements through control and monitoring tools that provide a global view of the network. With this purpose, we provide an overview of relevant Software Defined Networking (SDN) related approaches, and we describe an architecture based on OpenFlow that establishes different types of flows according to their needs and the network status. We present the implementation of the architecture and evaluate its capabilities using the Mininet network emulator.
2014 Scientific-Technical Contributions
2014 International IEEE Symposium on Precision Clock Synchronization for Measurement, Control and Communication (ISCPS 2014)
Title
Nanosecond Accuracy using SoC Platforms
Abstract
n this work, the implementation of IEEE 1588 functionalities on new Xilinx Zynq-7000 All Programmable SoC device is explored. An experimental set-up based on two Zynq commercial low-cost boards, with different PTP master and slave implementations has been analysed, taking benefit from the flexibility of the SoC all programmable devices. The explored features go from the only-software versions aided by the IEEE 1588-aware GMACs embedded in the processor sections to the high-accuracy solutions that combine the IEEE1588 hardware stuff of these modules with custom PTP IP cores in the FPGA sections of the devices. The results obtained from this analysis show excellent accuracy results, in the range of few nanoseconds and also standard deviation of less than 10 nanoseconds.
Link
XXIX Conference on Design of Circuits and Integrated Systems (DCIS 2014)
Title
FPGA Implemented Cut-Through vs Store-and-Forward Switches for Reliable Ethernet Networks
Abstract
In this paper, the latency times offered by two COTS IEC 62439-3 switch IP cores implementable on FPGAs have been compared. The first one, combines Cut-Through with Store-and-Forward switching architectures. The second IP is based only on Store-and-Forward switching technique. The analysis shows that a custom architecture that combines Cut-Through with Store-and-Forward approaches and takes advantage from Reconfigurable Technology offers the best latency times under any circumstance. This parameter is critical for the applications and sectors addressed in these new Reliable Ethernet protocols. Additionally, both IPs have been compared attending other features and resources required for their implementation. This comparison shows that a specifically designed architecture for the protocols specified in IEC 62439-3 offers excellent latency time and requires less resources than traditional Store-and-Forward ones.
39th Annual Conference of the IEEE Industrial Electronics Society
Title
SHA-3 based Message Authentication Codes to Secure IEEE 1588 Synchronization Systems
Abstract
Since the publication of IEEE 1588-2008 standard, the interest in giving cyber-security to Precision Time Protocol (PTP) traffic has increased. Therefore, several researches regarding security vulnerabilities and possible implementation improvements can be found in the literature. Particularly, SHA-1 and SHA-2 based MAC algorithms specified in the standard have already been proved to be suboptimal. In this paper, the utilization of new SHA-3 based MAC is proposed and both AES-128 and SHA-3 hardware implementations are compared in the context of PTP networks.
Link
Title
System-on-Chip Implementation of Reliable Ethernet Networks Nodes
Abstract
Reliable Ethernet Networks are gaining acceptance for many Industrial Automation applications. However, the diversity and variety of emerging Ethernet based Industrial Protocols make difficult for the Industry the selection of the technology to implement them. Furthermore, the continue evolution of the standards and their combination increment the risk in the engineering decisions. This need for flexibility combined with the need for hardware processing make FPGAs and reconfigurable devices in general, the best candidates to implement network devices and equipments able to deal with these issues. In this work, 3 architectures for Reliable Network Devices that support HSR and PRP protocols are presented. These architectures benefit from cutting-edge 28nm silicon fabrication reconfigurable technology combined with on-chip ARM processors and peripheral. One of the proposed architectures is implemented following a Design Flow that integrates 3 complex EDA tools and a third-party IP to achieve a full operative Reliable Networking Device with HSR and PRP processing capabilities.
Link
Title
Memory Requirements Analysis for PRP and HSR Hardware Implementations on FPGAs
Abstract
The IEC62439-3 defines two ways to obtain a high availability automation network: Parallel Redundancy Protocol (PRP) and High-availability Seamless Redundancy (HSR). In order to do that, those methods include different paths to send information frames from source to destination and add a redundancy field to the frames. Nodes in the network must remember arrived frames so as to manage the duplicated information. In this paper the requirements of memory needed for a hardware implementation are analyzed.
Link
Title
Duplicate and Circulating Frames Discard Methods for PRP and HSR (IEC62439-3)
Abstract
Parallel Redundancy Protocol (PRP) and High-availability Seamless Redundancy (HSR), defined in the IEC62439-3 about high availability automation networks and proposed as reference network topologies for substation communication networks by IEC61850, assure the upkeep of the communication when an error in a network occurs. Those methods consist in sending information duplicated through different and independent paths; so that nodes must be capable to eliminate the duplicated information circulating in the network. This paper analyzes ways to do the discard of those frames, which is crucial for a good implementation of the standard.
Link
September 2013
39th Annual Conference of the IEEE Industrial Electronics Society (IECON 2013)
Title
PRP and HSR Version 1 (IEC 62439-3 Ed.2), Improvements and a Prototype Implementation.
Abstract
The IEC62439-3: Industrial communication networks – High availability automation networks – Part 3: Parallel Redundancy Protocol (PRP) and High-availability Seamless Redundancy (HSR), defines two protocols which provides zero time recovery against a failure in the network. The first edition of the standard was published in 2010, and two years after a second edition has been published in July 2012. There have been some improvements which explain this actualization and an amendment between versions. This paper presents the most remarkable improvements included, others susceptible of being included and a software prototype to be run in PCs and/or FPGAs which implements this new version of the protocols.
Title
Memory Requirements Analysis for PRP and HSR Hardware Implementations on FPGAs.
Abstract
The IEC62439-3 defines two ways to obtain a high availability automation network: Parallel Redundancy Protocol (PRP) and High-availability Seamless Redundancy (HSR). In order to do that, those methods include different paths to send information frames from source to destination and add a redundancy field to the frames. Nodes in the network must remember arrived frames so as to manage the duplicated information. In this paper the requirements of memory needed for a hardware implementation are analyzed.
Title
Duplicate and Circulating Frames Discard Methods for PRP and HSR (IEC62439-3).
Abstract
Parallel Redundancy Protocol (PRP) and High-availability Seamless Redundancy (HSR), defined in the IEC62439-3 about high availability automation networks and proposed as reference network topologies for substation communication networks by IEC61850, assure the upkeep of the communication when an error in a network occurs. Those methods consist in sending information duplicated through different and independent paths; so that nodes must be capable to eliminate the duplicated information circulating in the network. This paper analyzes ways to do the discard of those frames, which is crucial for a good implementation of the standard.
Title
High-availability Seamless Redundancy for Train Ethernet Consist Network.
Abstract
The Train Communication Network standard (TCN) have more than 10 year and now is evolving to the use of Ethernet. But there is necessary to adapt Ethernet to critical applications. In this sense, a new redundancy protocol, the High availability Seamless Redundancy (HSR) protocol can help to achieve the requirements. Most important features of the HSR are analyzed and the implementation of a HSR IP core module is presented.
System-on-Chip Implementation of Reliable Ethernet Networks Node.
Abstract
Reliable Ethernet Networks are gaining acceptance for many Industrial Automation applications. However, the diversity and variety of emerging Ethernet based Industrial Protocols make difficult for the Industry the selection of the technology to implement them. Furthermore, the continue evolution of the standards and their combination increment the risk in the engineering decisions. This need for flexibility combined with the need for hardware processing make FPGAs and reconfigurable devices in general, the best candidates to implement network devices and equipments able to deal with these issues. In this work, 3 architectures for Reliable Network Devices that support HSR and PRP protocols are presented. These architectures benefit from cutting-edge 28nm silicon fabrication reconfigurable technology combined with on-chip ARM processors and peripheral. One of the proposed architectures is implemented following a Design Flow that integrates 3 complex EDA tools and a third-party IP to achieve a full operative Reliable Networking Device with HSR and PRP processing capabilities.
Title
SHA-3 based Message Authentication Codes to Secure IEEE 1588 Synchronization Systems.
Abstract
Since the publication of IEEE 1588-2008 standard, the interest of researchers in giving cyber-security to PTP traffic has increased and therefore, several articles regarding security vulnerabilities and possible implementation improvements can be found in the literature. Particularly, SHA-1 and SHA-2 based MAC algorithms specified in the standard have already been proved to be suboptimal. In this paper, the utilization of new SHA-3 based MAC is proposed and both AES-128 and SHA-3 hardware implementations are compared in the context of PTP networks.
22nd IEEE International Symposium on Industrial Electronics (ISIE). IEEE
Title
IEEE 1588 Transparent Clock Architecture for FPGA-based Network Devices.
Abstract
Apart from traditional test and measurement systems where clock synchronization is required, new emerging application areas like SmartGrids and 4G cellular mobile backhaul networks present strong timing constraints in terms of precise time synchronization. Precision Time Protocol (PTP), as defined in IEEE 1588 standard, offers sub-microsecond synchronization using conventional Ethernet networks. Thus, its acceptance is heavily increasing. However, the protocol performance was reduced in large cascaded networks with varying latencies. This drawback was later softened by the second version of the standard with the introduction of the Transparent Clock (TC) device. In this paper, a general overview of PTPv2 and the utilization of TCs is outlined. The main contribution is a new TC architecture for a FPGA-based network device that benefits from reconfigurable devices flexibility.
Link
June 2013
A summary of the work named “Reliability Measurement of FPGA Implementations on Software-Designed Radio Platforms” presented at the SDR-WInnComm-Europe 2013 (Munich, Germany).
Reliability Measurement of FPGA Implementations
on Software-Defined Radio Platforms
Cutting-edge Software-Defined Radio Platforms for Tactical Radios are designed according strict standards to be functional on harsh environment. Good examples of these standards are VPX (VITA 46) and VPX REDI. These platforms, from the system- level point of view, are heterogeneous systems composed of GPUs, ASICs and FPGAs.
The Reliability Measurement of these systems is a concern, and research activity in this field is very active. On one hand, in order to ensure functionality in critical missions and on the other hand, to fulfill the requirements set in different certification standards. The platform vendor of final customer would need to address the safety and reliability requirements for the hardware and software implementations. For the hardware part, as an example, well known standards are DO-254 for Airborne systems, IEC 61508 for Safety-critical Systems or specific MIL certifications for Defense applications. For software part, the reliability is also covered by specific standards like DO-178.
In many of these cases, the platform vendor needs to offer a reliability measurement in terms of MTBF parameter or equivalent (as Lambda). These parameters are provided by the microelectronic circuit’s manufacturer for ASICs or GPUs devices. However, the reliability analysis of FPGA implemented designs is not seamless. Each design implemented on an FPGA has different layout inside the device and it require different number of resources and will be placed and routed using different internal locations. This leads to different behavior of the implementation against Single-Event Effects, the most important source of Faults on SRAM based FPGAs. Furthermore, the SRAM based FPGAs are gaining more and more importance on cutting-edge SDR platforms.
From the SDR point-of-view, these effects could lead to loose the communication link. For mission-critical systems, this risk must be quantified and mitigated up to a reasonable level. Thus, a lot of research effort is being developed to mitigate SEU effect and to ensure the requested reliability level of a given implementation on a FPGA.
This presentation focuses on a novel methodology valid to measure experimentally the reliability of design implementations on FPGAs. In the first Section, an introduction to the Reliability on Electronic devices will be addressed, focusing on reconfigurable devices. The next section summarizes the Fault Tolerance and Error Mitigation techniques that can be used to ruggedized FPGA implemented designs. In the third Section, a Methodology to Experimentally Measure the reliability of a given FPGA implementation is addressed and it is applied to two designs common on SDR applications.
The first analysis presented is the resilience against SEU effects of Cryptography Cipher Blocks implemented on FPGAs. The robustness of AES, DES and TwoFish is measured and compared.
The second analysis is a study of the effect of different approaches of Triple Modular Redundancy applied to FPGA standard on-chip bus. For SDR designs implemented on FPGA, these on-chip interconnection means are critical. They are used to link the different Digital-Signal Processing and control modules involved in the design. Furthermore, on-chip interconnection standards are playing a vital role on the heterogeneous SDR implementations (GPUs, DSPs and FPGAS) and on standardization (CORBA hardware layers).
The presentation also summarizes some COTS hardware that can be used to implement designs specifically protected against SEU effects.
The presentation ends with the conclusions and future work in this field.
Full presentation here:
Reliability Measurement of FPGA Implementations on Software-Designed Radio Platforms